Split gate flash memory cell with ballistic injection

ABSTRACT

A split floating gate flash memory cell is comprised of source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The sections of the floating gate are isolated from each other by a depression in the control gate. The cell is programmed by creating a positive charge on the floating gate and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the floating gate section adjacent to the pinched off channel region.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to memory devices and inparticular the present invention relates to split gate memory cells.

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal, semiconductor,integrated circuits in computers or other electronic devices. There aremany different types of memory including random-access memory (RAM),read only memory (ROM), dynamic random access memory (DRAM), synchronousdynamic random access memory (SDRAM), and flash memory. One type offlash memory is a nitride read only memory (NROM). NROM has some of thecharacteristics of flash memory but does not require the specialfabrication processes of flash memory. NROM integrated circuits can beimplemented using a standard CMOS process.

Flash memory devices have developed into a popular source ofnon-volatile memory for a wide range of electronic applications. Flashmemory devices typically use a one-transistor memory cell that allowsfor high memory densities, high reliability, and low power consumption.Common uses for flash memory include personal computers, personaldigital assistants (PDAs), digital cameras, and cellular telephones.Program code and system data such as a basic input/output system (BIOS)are typically stored in flash memory devices for use in personalcomputer systems.

The performance of flash memory transistors needs to increase as theperformance of computer systems increases. To accomplish a performanceincrease, the transistors can be reduced in size. This has the effect ofincreased speed with decreased power requirements.

However, a problem with decreased flash memory size is that flash memorycell technologies have some scaling limitations due to the high voltagerequirements for program and erase operations. As MOSFETs are scaled todeep sub-micron dimensions, it becomes more difficult to maintain anacceptable aspect ratio. Not only is the gate oxide thickness scaled toless than 10 nm as the channel length becomes sub-micron but thedepletion region width and junction depth must be scaled to smallerdimensions. The depletion region or space charge width can be madesmaller by increasing the substrate or well doping. However, it isextremely difficult to scale the junction depths to 100nm-200 nm (1000 Åto 2000 Å) since these are doped by ion implantation and diffusion.

Another problem with flash memories is program speed. Depending onthreshold voltage levels, programming times in tenths of a second ormore is not uncommon.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art fora more scalable, higher performance flash memory transistor.

SUMMARY

The above-mentioned problems with performance, scalability, and otherproblems are addressed by the present invention and will be understoodby reading and studying the following specification.

The present invention encompasses a flash memory cell comprising asubstrate that has a pair of doped regions acting as source/drainregions. The source/drain regions are linked by a channel in thesubstrate.

A split floating gate is formed over the substrate and comprises aplurality of floating gate sections. A first floating gate sectionestablishes a virtual source/drain region in the channel when a drainvoltage is applied to an adjacent source/drain region. The virtualsource/drain region has a lower threshold voltage than the remainingportion of the channel.

A control gate is formed over the split floating gate and includes adepression formed between the plurality of sections such that thedepression electrically isolates the floating gate sections. The controlgate comprises a wordline linking other flash memory cells of a memorycell array.

Further embodiments of the invention include methods and apparatus ofvarying scope.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-sectional view of one embodiment of a planar splitgate flash memory cell of the present invention.

FIG. 2 shows a cross-sectional view of one embodiment of a verticalsplit gate flash memory cell of the present invention.

FIG. 3 shows an electrical schematic view of the embodiments of FIGS. 1and 2.

FIG. 4 shows a plot of one embodiment of the potential energy forelectrons along the surface of the embodiment of FIG. 1.

FIGS. 5A and 5B show a cross-sectional view of one embodiment of a readoperation of the present invention in accordance with the embodiment ofFIG. 1.

FIGS. 6A and 6B show a cross-sectional view of another embodiment of aread operation of the present invention in accordance with theembodiment of FIG. 1.

FIGS. 7A-7D show a cross-sectional view of one embodiment of afabrication method of the present invention in accordance with theembodiment of FIG. 1.

FIGS. 8A-8E show a cross-sectional view of one embodiment of afabrication method of the present invention in accordance with theembodiment of FIG. 2.

FIG. 9 shows a block diagram of an electronic system of the presentinvention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings that form a part hereof and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims and equivalents thereof.

FIG. 1 illustrates a cross-sectional view of one embodiment of a planarsplit gate flash memory cell of the present invention. The cell iscomprised of a substrate 106 that has two n+ doped regions 101 and 102that act as source/drain regions. The function of the region 101 or 102is determined by the direction of operation of the memory cell. In theembodiment of FIG. 1, the substrate 106 is a p-type material and thesource/drain regions 101 and 102 are n-type material. However, alternateembodiments may have an n-type substrate with p-type source/drainregions.

A channel region 110 is formed between the source/drain regions 101 and102. During a program operation, as is well known in the art, theelectrons are injected from a pinched off area of the channel region 110to a floating gate 103 or 104. The electrons flow in the oppositedirection during an erase operation.

The split floating gate 103 and 104, typically made of dopedpolysilicon, is disposed over the channel region 110. The floating gatesections 103 and 104 are electrically isolated from the substrate by adielectric layer. For example, a gate oxide can be formed between thefloating gate 103 and 104 and the channel region 110.

A control gate 105 is located over the floating gate 103 and 104 and canalso be made of doped polysilicon. The control gate 105 is electricallyseparated from the floating gates 103 and 104 by another dielectriclayer. Thus, the floating gate 103 and 104 is “floating” in dielectricso that they are insulated from both the channel region 110 and thecontrol gate 105. A depression portion of the control gate 105physically separates or “splits” the floating gate 103 and 104 such thattwo charge storage areas are created.

In operation, the memory cell of the present invention employs ballisticdirection injection to perform a programming operation. The ballisticdirection injection provides lower write times and currents.

The ballistic direction injection is accomplished by initiallyover-erasing the cell. This may be done during a functional test. Theover-erase operation leaves the floating gate sections 103 and 104 withan absence of electrons (i.e., in a positive charge state) and creatinga “virtual” source/drain region 113 near the source/drains regions. Thevirtual source/drain region 113 has a lower threshold voltage than thecentral part of the channel 110 and is either an ultra thin sheet ofelectrons or a depleted region with a low energy or potential well forelectrons.

When the transistor is turned on with an applied drain voltage, avariation in potential energy is created along the surface of thesemiconductor, as will be illustrated later with reference to FIG. 4. Apotential well or minimum for electrons exists due to the positivefloating gate charge. When the transistor is turned on, these potentialenergy minimums for electrons cause a higher density of electrons nearthe source. Thus the channel pinches off further away 113 from the drain101 than normal. The length of the pinched-off region 113 is determinedby the length of the floating gates that have sub-lithographic minimaldimensions. Hot electrons accelerated in the narrow region 113 near thedrain 101 become ballistic and are directly injected onto the floatinggate 103.

In one embodiment, this pinched-off region 113 is in a range of 10-40 nm(100-400 Å). Alternate embodiments have different ranges depending onfloating gate length.

The flash memory transistor of the present invention is symmetrical andcan be operated in either direction to create two possible storageregions when operated in a virtual ground array. Therefore, the aboveoperation description can be applied to the operation of the transistorwhen the remaining source/drain region 102 is biased such that itoperates as a drain region.

In one embodiment, a substrate or well voltage, V_(sub), is used toassist during a program operation. The substrate bias enables thefloating gates to store injected electrons in excess of those that wouldbe stored without the substrate bias. Without the bias, the programprocess is self-limiting in that when enough electrons have beencollected on a floating gate, the gate tends to repel any furtherelectrons. The substrate bias results in a significant negative chargeto be written to the floating gate. The substrate bias is not requiredfor proper operation of the embodiments of the present invention.

In one embodiment, the substrate bias is a negative voltage in a rangeof −1V to −2V. Alternate embodiments use other voltages.

FIG. 2 illustrates a cross-sectional view of one embodiment of avertical split gate flash memory cell of the present invention. Thetransistor is comprised of a substrate 206 that includes a plurality ofdoped regions 201 and 202 that act as source/drain regions. In oneembodiment, the substrate is a p-type material and the doped regions aren-type material. Alternate embodiments use an n-type substrate withopposite type doped regions 201 and 202.

The substrate forms a pillar between two floating gates 203 and 204.This provides electrical isolation of the floating gates 203 and 204. Acontrol gate 205 is formed over the floating gates 203 and 204 andsubstrate pillar.

A channel region 210 is formed between the floating gates 203 and 204.Additionally, as in the planar embodiment of FIG. 1, a virtualsource/drain region 213 is formed by an over-erase operation leaving thefloating gates 203 and 204 with an absence of electrons (i.e., in apositive charge state). However, in the vertical split gate embodiment,the virtual source/drain region 213 and channel region 210 aretwo-dimensional in that they wrap around the corners of the substratepedestal.

The operation of the vertical split gate transistor embodiment of FIG. 2is substantially similar to the operation described above for the planarembodiment. A drain bias is applied to one of the source/drain regions201 or 202 that causes the channel region 210 nearest the drain to pinchoff 213 further away from the drain 201 than normal. Hot electronsaccelerated in the narrow region 213 near the drain 201 become ballisticand are directly injected onto the floating gate 203. The embodiment ofFIG. 2 is also symmetrical and can be operated in either direction suchthat two storage regions 203 or 204 are possible when operated in avirtual ground array.

In one embodiment, a substrate or well voltage, V_(sub), is used toassist during a program operation. The substrate bias enables thefloating gates to store injected electrons in excess of those that wouldbe stored without the substrate bias. In one embodiment, the substratebias is a negative voltage in a range of −1 to −2 V. Alternateembodiments use other voltages. The substrate bias is not required forproper operation of the embodiments of the present invention.

Ballistic direction injection is easiest to achieve in a devicestructure where part of the channel is vertical as illustrated in theembodiment of FIG. 2. Lower write current and times are used since thegeometry is conducive to hot electrons being accelerated by the electricfields. Hot electrons coming off of the pinched off end of the channelcan be injected onto the floating gates without undergoing anycollisions with the atoms in the lattice.

FIG. 3 illustrates an electrical schematic view of both the planar andvertical split gate embodiments described in FIGS. 1 and 2. The memorycell symbol shows the transistor 300 with the substrate or well bias306. The virtual ground array is the bit/data lines 301 and 302. Theseare illustrated in FIGS. 1 and 2 as the source/drain regions 101, 102,201, and 202, respectively. The word address line 305 is illustrated inFIGS. 1 and 2 as the control gate 105 and 205, respectively.

FIG. 4 illustrates a plot of one embodiment of the potential energy forelectrons along the surface of the planar embodiment of FIG. 1. The plotfor the vertical split gate embodiment is substantially similar and isnot illustrated herein in the interest of brevity.

The plot of FIG. 4 shows that the electron potential energy increases asthe distance increases from the drain of the transistor 400. Theballistic transport region 401 is indicated adjacent the drain regionand is indicated as 10-40 nm wide. However, alternate embodiments mayuse different ballistic transport region widths, depending on the widthof the floating gate. The electron potential energy sharply drops at thesecond floating gate and drops further 403 in response to the sourceregion.

FIGS. 5A and 5B illustrate a read operation in one direction for theplanar embodiment transistor of the present invention. Referring to FIG.5A, the left side source/drain region 501 is grounded while the rightside source/drain region 502 acts as a drain with a drain voltageapplied (V_(DS)). A relatively smaller gate voltage (V_(GG)), nearthreshold, is applied to turn on the transistor. If there are noelectrons stored on the left floating gate 505, the channel near thesource region 501 turns on and the channel conducts such that draincurrent IDS flows.

FIG. 5B illustrates an embodiment where the left floating gate 505 haselectrons stored such that the portion of the channel near the sourceregion 501 does not turn on and the channel will not conduct. Thisresults in no drain current flow. A large drain voltage is applied tofully deplete the region 510 near the drain 502 so that the charge stateof the floating gate 506 on the right side cannot determine theconductivity state of the cell.

FIGS. 6A and 6B illustrate a read operation in the opposite directionthan that illustrated in FIGS. 5A and 5B. In this embodiment, asillustrated in FIG. 6A, the right source/drain region 602 is groundedand a drain voltage is applied to the left source/drain region 601 thatis now acting as the drain.

A relatively smaller gate voltage (e.g., near threshold) is applied inorder to turn on the transistor. If no electrons are stored on the rightfloating gate 606, the portion of the channel near the source 602 turnson and the channel conducts. This results in a drain current I_(DS)flow.

FIG. 6B illustrates an embodiment where the right floating gate 606 hasstored electrons. In this embodiment, the channel near the source 602does not turn on and the channel will not conduct. This results in nodrain current flow. A large drain voltage, VDS, is applied to the drain601 to fully deplete the region 610 near the drain 601 so that thecharge state of the left floating gate 605 cannot determine theconductivity state of the cell.

FIGS. 7A-7D illustrate a cross-sectional view of one embodiment of afabrication method of the present invention in accordance with theplanar embodiment of FIG. 1. The following fabrication methods in bothFIGS. 7 and 8 refer to a p-type substrate and n-type conductivity dopedregions. However, the present invention is not limited to this type oftransistor.

The fabrication method illustrated in FIG. 7A begins with a p-typeconductivity silicon substrate 700 that is doped in a plurality ofsource/drain regions 701 and 702 to n-type conductivity material. Eachtransistor is comprised of a source region and a drain region where theorientation is determined by the direction of operation of thetransistor.

An oxide layer 705 is deposited on the surface of the substrate 700. Apolysilicon layer 707 is deposited on top of the oxide layer 705. Asdiscussed subsequently, the polysilicon layer 707 eventually becomes thefloating gates that are insulated from the substrate by the oxide layer705.

An oxide pillar 710 is grown on top of the polysilicon layer 707substantially between the n+regions 701 and 702. Nitride areas 711 and712 are formed on either side of the oxide pillar 710. In oneembodiment, each nitride area is in a range of 10-40 nm wide. A sidewallprocess that is well known in the art is used to define thesesublithographic in a 100 nm technology and etch the short floatinggates.

FIG. 7B shows that the oxide pillar is removed to leave the nitrideareas 711 and 712 that protect the areas in the polysilicon layer thatare to become the floating gates. FIG. 7C etches away the nitride areasas well as the portions of the polysilicon layer that is exposed. Thisleaves the two floating gates 720 and 721. Another oxide layer 725 isthen formed over the floating gates 720 and 721.

FIG. 7D shows that a layer of polysilicon 730 is deposited over theupper oxide layer 725. The polysilicon layer 730 forms the control gatefor the transistor. The virtual ground array configuration insures thatall components of the device structure are self-aligned and that thereare no critical alignment steps.

FIGS. 8A-8E show a cross-sectional view of one embodiment of afabrication method of the present invention in accordance with thevertical, split gate embodiment of FIG. 2. The process begins with asilicon p-type substrate 800 on which an oxide layer 801 and a nitridelayer 803 are formed.

A trench 805 is then etched into the substrate and through the two upperlayers 801 and 803. FIG. 8B shows that an n+ doped region 807 is formedunder the trench to act as a source/drain region 807. FIG. 8C shows thata layer of oxide 810 is deposited on the substrate and in the trench.The split gates are formed by a sidewall process growing polysiliconareas 815 and 816 on the inside sidewalls of the oxide layer 810 in thetrench. The length of the split gates 815 and 816 are defined by thedepth of the trench and by the use of the sidewall process. The sidewallprocess is well known in the art and is not discussed further.

FIG. 8D shows an oxide layer 820 is deposited on top of the floatinggates in the trench and over the oxide layer outside the trench. FIG. 8Eillustrates the deposition of a polysilicon layer 823 that acts as thecontrol gate for the transistor.

While the fabrication methods illustrated in FIGS. 7 and 8 focus on onlyone flash transistor, it is well known in the art that this fabricationmethod is used to fabricate millions of transistors on an integratedcircuit.

FIG. 9 illustrates a functional block diagram of a memory device 900that can incorporate the flash memory cells of the present invention.The memory device 900 is coupled to a processor 910. The processor 910may be a microprocessor or some other type of controlling circuitry. Thememory device 900 and the processor 910 form part of an electronicsystem 920. The memory device 900 has been simplified to focus onfeatures of the memory that are helpful in understanding the presentinvention.

The memory device includes an array of flash memory cells 930 that canbe floating gate flash memory cells. The memory array 930 is arranged inbanks of rows and columns. The control gates of each row of memory cellsis coupled with a wordline while the drain and source connections of thememory cells are coupled to bitlines. As is well known in the art, theconnection of the cells to the bitlines depends on whether the array isa NAND architecture or a NOR architecture. The memory cells of thepresent invention can be arranged in either a NAND or NOR architectureas well as other architectures.

An address buffer circuit 940 is provided to latch address signalsprovided on address input connections A0-Ax 942. Address signals arereceived and decoded by a row decoder 944 and a column decoder 946 toaccess the memory array 930. It will be appreciated by those skilled inthe art, with the benefit of the present description, that the number ofaddress input connections depends on the density and architecture of thememory array 930. That is, the number of addresses increases with bothincreased memory cell counts and increased bank and block counts.

The memory device 900 reads data in the memory array 930 by sensingvoltage or current changes in the memory array columns usingsense/buffer circuitry 950. The sense/buffer circuitry, in oneembodiment, is coupled to read and latch a row of data from the memoryarray 930. Data input and output buffer circuitry 960 is included forbi-directional data communication over a plurality of data connections962 with the controller 910. Write circuitry 955 is provided to writedata to the memory array.

Control circuitry 970 decodes signals provided on control connections972 from the processor 910. These signals are used to control theoperations on the memory array 930, including data read, data write, anderase operations. The control circuitry 970 may be a state machine, asequencer, or some other type of controller.

The flash memory device illustrated in FIG. 9 has been simplified tofacilitate a basic understanding of the features of the memory. A moredetailed understanding of internal circuitry and functions of flashmemories are known to those skilled in the art.

CONCLUSION

In summary, a planar flash memory device uses a combination of veryshort split floating gate regions and substrate bias to accelerateelectrons near a drain region during a write operation. In oneembodiment, the floating gate regions are 10-40 nm in length. Using theballistic direction injection, electrons can be accelerated over a shortdistance and easily overcome the silicon-oxide interface potentialbarrier and be injected onto the floating gate.

In the case of flash memory devices where at least part of the channelis vertical, the geometry is more favorable for ballistic transportelectrons being incident on the silicon-oxide interface and beingdirectly injected over this barrier onto the floating gate. Theseelectrons will not undergo collisions with the lattice atoms. Writecurrents and times will be lower and substrate bias is not required.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the invention. It is manifestly intended that thisinvention be limited only by the following claims and equivalentsthereof.

1. A flash memory cell comprising: a substrate having a pair of dopedregions, the pair of doped regions being linked by a channel in thesubstrate; a split floating gate comprising a plurality of sections suchthat a first floating gate section establishes a virtual source/drainregion in the channel, the virtual source/drain region having a lowerthreshold voltage than a remaining portion of the channel; and a controlgate formed over the split floating gate and comprising a depressionformed between the plurality of sections such that the depressionelectrically isolates the floating gate sections.
 2. The cell of claim 1wherein the split floating gate is in a vertical configuration.
 3. Thecell of claim 1 and further including a substrate bias connection thatis capable of applying a bias to the substrate.
 4. The cell of claim 3wherein the bias is in a range of −1V to −2V.
 5. The cell of claim 2wherein the channel between the vertical split floating gate sections istwo-dimensional.
 6. The cell of claim 1 wherein the virtual source/drainregion is established in response to an absence of electrons on thefirst floating gate section.
 7. The cell of claim 1 wherein thesubstrate is a p-type silicon material and the doped regions are ann-type silicon material.
 8. A flash memory cell comprising: a substratehaving a pair of source/drain regions, the pair of source/drain regionsbeing linked by a channel; a planar split floating gate comprising aplurality of floating gate sections such that a first floating gatesection establishes a virtual source/drain region in the channel, thevirtual source/drain region having a lower threshold voltage than aremaining portion of the channel; and a control gate formed over theplanar split floating gate and comprising a depression formed betweenthe plurality of floating gate sections such that the depressionelectrically isolates the floating gate sections.
 9. The cell of claim 7wherein the virtual source/drain region is established in response to adrain voltage being applied to a first source/drain region adjacent thevirtual source/drain region.
 10. The cell of claim 8 and furtherincluding a first oxide layer between the substrate and the planar splitfloating gate and a second oxide layer between the planar split floatinggate and the control gate.
 11. The cell of claim 8 wherein the virtualsource/drain region has a length in a range of 10-40 nm.
 12. The cell ofclaim 8 wherein the virtual source/drain region is established inresponse to a positive charge on the first floating gate section.
 13. Aflash memory cell comprising: a substrate having a pair of source/drainregions, each source/drain region located under a trench in thesubstrate, the pair of source/drain regions being linked by atwo-dimensional channel that follows a surface of a pillar formedbetween the trenches; a vertical split floating gate comprising aplurality of floating gate sections that are separated by the pillar, afirst floating gate section capable of establishing a virtualsource/drain region in the channel adjacent to the first floating gate,the virtual source/drain region having a lower threshold voltage than aremaining portion of the channel; and a control gate formed over thevertical split floating gate.
 14. The cell of claim 13 wherein adepression of the control gate is formed in the trench to separate afirst flash memory cell from a second flash memory cell.
 15. The cell ofclaim 13 wherein the virtual source/drain region is 100-400 Å in length.16. The cell of claim 13 wherein the source/drain regions link aplurality of memory cells in a virtual ground array configuration.
 17. Aflash memory cell array comprising: a plurality of memory cells coupledtogether through wordlines and bitlines, each cell comprising: asubstrate having a pair of source/drain regions, the pair ofsource/drain regions being linked by a channel in the substrate, eachsource/drain region coupled to a different bitline; a split floatinggate comprising a plurality of sections such that a first floating gatesection establishes a virtual source/drain region in the channeladjacent to the first floating gate section, the virtual source/drainregion having a lower threshold voltage than a remaining portion of thechannel; and a control gate formed over the split floating gate andcomprising a depression formed between the plurality of sections suchthat the depression electrically isolates the floating gate sections,the control gate coupled to the wordlines.
 18. The array of claim 17wherein the plurality of memory cells are configured in a NAND-typearchitecture.
 19. The array of claim 17 wherein the plurality of memorycells are configured in a NOR-type architecture.
 20. An electronicsystem comprising: a processor that generates memory control signals;and a flash memory cell array coupled to the processor and comprising aplurality of memory cells coupled together through wordlines andbitlines, each cell comprising: a substrate having a pair ofsource/drain regions, the pair of source/drain regions being linked by achannel in the substrate, each source/drain region coupled to adifferent bitline; a split floating gate comprising a plurality ofsections such that a first floating gate section establishes a virtualsource/drain region in the channel adjacent to the first floating gatesection, the virtual source/drain region having a lower thresholdvoltage than a remaining portion of the channel; and a control gateformed over the split floating gate and comprising a depression formedbetween the plurality of sections such that the depression electricallyisolates the floating gate sections, the control gate coupled to thewordlines.
 21. A method for writing to a flash memory cell comprising asplit floating gate located between a substrate having two source/drainregions and a control gate, the two source/drain regions linked by achannel in the substrate, the method comprising: creating a positivecharge on the floating gate; grounding a first source/drain region;applying a gate voltage to the control gate; and applying a drainvoltage to the second source/drain region such that ballistic directioninjection occurs in a virtual source/drain region of the channeladjacent a section of the split floating gate.
 22. The method of claim21 and further including applying a substrate bias to the substrate. 23.The method of claim 22 wherein the substrate bias is a negative voltage.24. The method of claim 21 wherein creating the positive charge includesovererasing the flash memory cell.
 25. A method for writing to a flashmemory cell comprising a split floating gate located between a substratehaving two source/drain regions and a control gate, the two source/drainregions linked by a channel in the substrate, the method comprising:creating a positive charge on the floating gate; grounding a firstsource/drain region; applying a gate voltage to the control gate; andapplying a drain voltage to the second source/drain region such that thechannel is pinched off a distance in a range of 10-40 nm from the secondsource/drain region and adjacent to a section of the split floatinggate.